PIC18LF66K80-I/PT【PDF 104/351 页】MCU PIC ECAN 64KB FLASH 64TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3841

100页 101页 102页 103页 [104页]105页 106页 107页 108页

PIC18F66K80 FAMILY

DS39977F-page 192

2010-2012 Microchip Technology Inc.

11.9

Parallel Slave Port

PORTD can function as an 8-bit-wide Parallel Slave

Port (PSP), or microprocessor port, when control bit,

PSPMODE (PSPCON<4>), is set. The port is asyn-

chronously readable and writable by the external world

through the RD control input pin (RE0/AN5/RD) and

WR control input pin (RE1/AN6/C1OUT/WR).

The PSP can directly interface to an 8-bit micro-

processor data bus. The external microprocessor can

read or write the PORTD latch as an eight-bit latch.

Setting

bit,

PSPMODE,

enables

port

pin,

RE0/AN5/RD,

the

input,

RE1/AN6/C1OUT/WR to be the WR input and

RE2/AN7/C2OUT/CS to be the CS (Chip Select)

input. For this functionality, the corresponding data

direction bits of the TRISE register (TRISE<2:0>)

must be configured as inputs (= 111).

A write to the PSP occurs when both the CS and WR

lines are first detected low and ends when either are

detected high. The PSPIF and IBF flag bits (PIR1<7>

and PSPCON<7>, respectively) are set when the write

ends.

A read from the PSP occurs when both the CS and RD

lines are first detected low. The data in PORTD is read

out and the OBF bit (PSPCON<6>) is set. If the user

writes new data to PORTD to set OBF, the data is

immediately read out, but the OBF bit is not set.

When either the CS or RD line is detected high, the

PORTD pins return to the input state and the PSPIF bit

is set. User applications should wait for PSPIF to be set

before servicing the PSP. When this happens, the IBF

and OBF bits can be polled and the appropriate action

taken.

The timing for the control signals in Write and Read

modes is shown in Figure 11-4 and Figure 11-5,

respectively.

FIGURE 11-3:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE PORT)

Note:

The Parallel Slave Port is available only on

40/44-pin and 64-pin devices.

Data Bus

WR LATD

RDx

RD PORTD

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

Note:

The I/O pin has protection diodes to VDD and VSS.

PORTD

RD LATD

Data Latch

TRIS Latch

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式